1. Field of the Invention
The present invention relates to a semiconductor device equipped with an output circuit for latching data in response to a clock and enhancing the driving power of output data signal.
2. Description of the Related Art
FIG. 11(A) is a time chart showing a relation between DATA and a clock CLK, wherein the data is one outputted from an output circuit built in a semiconductor device of this type, for example DRAM. In a circuit receiving the DATA, since the DATA is held in response to an edge of the clock CLK, the DATA has to be definite on the edge.
An indefinite-data time B increases while a definite-data time A=Txe2x88x92B, wherein T represents a cycle time of the clock CLK, decreases due to variations in process, temperature and power supply voltage of the semiconductor device. For example, in a case of the clock CLK being 100 MHZ, since T is as short as T=10 ns, the indefinite-data time is necessary to be shorter in order to increase a clock frequency.
As shown in FIG. 11(B), if there is a phase difference xcfx86 between rising and falling edges of data signal relative to an edge of the clock CLK because of the above described causes, there arise a difference between duration""s of high and low levels, resulting in extending the indefinite-data time.
In the prior art, an output circuit was adjusted such that the phase difference xcfx86 was made smaller prior to shipment of a product (a semiconductor device).
However, since there are variations in temperature and power supply voltage in operation of respective products built in electronic equipment, there has been a problem that the indefinite-data time B becomes longer with increase in the phase difference xcfx86.
Accordingly, it is an object of the present invention to provide a semiconductor device which enables to shorten an indefinite-data time by automatically decreasing a phase difference between rising and falling edges of data signal relative to a clock edge.
In one aspect of the present invention, there is provided a semiconductor device comprising: an output circuit, having a clock input to receive a clock, having a data input to receive an input data, having a data output providing the input data as an output data in response to the clock, having a control input to receive a control signal for adjusting an output timing of the output data; a replica circuit of the output circuit, having a clock input to receive the clock, having a data input to receive a cyclically inverted input dummy data, the input dummy data being in synchronism with the clock, having a data output providing the dummy data as an output dummy data in response to the clock, having a control input to receive the control signal for adjusting an output timing of the output dummy data; a dummy load circuit, receiving the output dummy data; and a control circuit, providing the control signal to make high and low level duration of the output dummy data provided from the dummy load circuit become equal to each other.
With this aspect, high and low level duration of the output of the replica circuit becomes almost equal to each other independently of variations in fabrication process parameters, temperature or power supply voltage of the semiconductor device, so that the indefinite-data time of the output of the output circuit is prevented from being longer. Therefore, the clock can be faster.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.